Development Timeline
| Milestone | Focus | Status |
|---|---|---|
| Foundation | Core architecture and dynamics | Completed |
| Representation | Internal structure formation | Completed |
| Validation | Subsystem stress testing | Completed |
| Competition | Multi-unit interaction dynamics | Completed |
| Edge | Hardware-optimized deployment | In progress |
Technical Highlights
- Local online learning without end-to-end backpropagation — no loss functions, no optimizer
- Hundreds of computational units competing in real-time under finite resource constraints
- No pre-training required — no labeled datasets, no offline preparation
- 35+ public datasets across 19 domains — each domain modelled and validated independently, no transfer assumed
- Over 1.8 million controlled experiment runs across multiple research lines
Multi-Channel Architecture
RailMind outputs through three parallel channels — each serving a distinct integration use case:
| Channel | Output | Use Case |
|---|---|---|
| Ch.1 Health Vector | Adaptive internal representation projected to compact diagnostic space | Fault detection and classification |
| Ch.2 Drift Gate | Zero-compute distribution shift detector | Alerts when the input distribution shifts |
| Ch.3 Raw State | Full internal representation | Custom downstream tasks and research |
Validation Breadth
Validated on 35+ public datasets across 19 domains. Each domain is modelled and validated independently — we do not assume transfer between domains.
| Domain | Named public datasets |
|---|---|
| Rotating machinery — bearings, gears | CWRU · Paderborn/KAT · XJTU-SY · FEMTO/PHM2012 · SEU · IMS · MFPT · HUST · KAIST · UORED · MCC5 · CITEF |
| Turbofan remaining-life | C-MAPSS (FD001–004) |
| Machine audio anomaly | DCASE (ToyCar / Fan) |
Under validation
| Domain | Named public datasets |
|---|---|
| Bridge structural health | Z24 · KW51 |
| Satellite telemetry | ESA-ADB SMAP · MSL |
| Video | CLIP-video · AI City · seg19 |
| Human activity recognition | UCI HAR |
Edge Performance
Production-verified performance on commodity hardware:
Runtime memory
Full configuration runtime memory: approximately 200 KB, including all PdM modules, with zero dynamic allocation.
MCU latency
L-tier configuration (not the full configuration): mean engine-step latency of 0.90 ms on an STM32F767 (Cortex-M7, 216 MHz).
Note: the memory and latency figures above correspond to different configurations and do not constitute a latency–memory pairing for a single configuration.
Zero heap allocation in the hot path — all static buffers. No garbage collection pauses, no fragmentation over 24/7 industrial deployment.
Drift Detection
Built-in distribution shift detection with zero additional computation:
- Detects distribution drift and sensor degradation as it happens
- Operating-condition changes are handled via explicit condition input (ConditionInput) — not inferred from the signal